ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 91
ds96-039wdsp
Manufacturer Part Number
ds96-039wdsp
Description
Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
Manufacturer
ETC-unknow
Datasheet
1.DS96-039WDSP.pdf
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DSP1628 Digital Signal Processor
10 Timing Characteristics for 2.7 V Operation
10.3 Reset Synchronization
* See Table 62 for input clock electrical requirements.
Note 1: CKO
Note 2: If the rising edge of RSTB (low to high) is captured instead by the falling edge of CKO (high to low), CKO and CKI will be in-phase
Table 70. Timing Requirements for Reset Synchronization Timing
89
Abbreviated Reference
RSTB
CKO
CKO
CKI*
at t5 + 2 x t6.
1
2
V
V
V
V
V
V
V
V
1
OH
OH
OL
OL
IH
IH
IL
IL
and CKO
t126
2
are two possible CKO states before reset. CKO is free-running.
Reset Setup (high to high)
Figure 13. Reset Synchronization Timing
t126
Parameter
t5 + 2 x t6
(continued)
Min
3
T/2 – 1
Max
Lucent Technologies Inc.
Unit
ns
February 1997
5-4011 (C).a
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