ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 54

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
5 Software Architecture
† Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-extended.
Table 23. Replacement Table for F3 ALU Instructions and F4 BMU Instructions
52
Barrel Shifter
Normalization and Exponent Computation
Bit Field Extraction and Insertion
Alternate Accumulator Set
Note: The bit field to be inserted or extracted is specified as follows. The width (in bits) of the field is the upper
Note: The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator.
aD, aT, aS
Replace
aD = aS >> IM16
aD = aS >> arM
aD = aS >> aS
aD = aS >>> IM16
aD = aS >>> arM
aD = aS >>> aS
aD = aS << IM16
aD = aS << arM
aD = aS << aS
aD = aS <<< IM16
aD = aS <<< arM
aD = aS <<< aS
aD = exp(aS)
aD = norm(aS, arM)
aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word.
aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle.
aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word.
aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle.
aD = insert(aS, IM16)
aD = insert(aS, arM)
aD = aS:aa0
aD = aS:aa1
IM16
arM
byte of the operand (immediate or arM), and the offset from the LSB is in the lower byte.
Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle.
Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle.
immediate
ar<0—3>
a0 or a1
Value
Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word.
Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.
Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.
Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word.
Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle.
Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle.
Arithmetic left shift
Arithmetic left shift
Arithmetic left shift
Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle.
Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle.
Detect the number of redundant sign bits in accumulator; 1-cycle.
Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.
Bit field insertion, field specified as immediate; 2-cycle, 2-word.
Bit field insertion, field specified in arM; 2-cycle.
(continued)
One of the two accumulators.
16-bit data, sign-, zero-, or one-extended as appropriate.
One of the auxiliary BMU registers.
†
†
†
by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
by arM (36-bit shift, 0s filled in); 1-cycle.
by aS (36-bit shift, 0s filled in); 2-cycle.
Meaning
Lucent Technologies Inc.
February 1997