ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 36

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
4 Hardware Architecture
4.12 JTAG Test Port
The DSP1628 uses a JTAG/ IEEE 1149.1 standard five-
wire test port (TDI, TDO, TCK, TMS, TRST) for self-test
and hardware emulation. An instruction register, a
boundary-scan register, a bypass register, and a device
identification register have been implemented. The de-
vice identification register coding for the DSP1628 is
shown in Table 41. The instruction register (IR) is 4 bits
long. The instruction for accessing the device ID is 0xE
(1110). The behavior of the instruction register is sum-
marized in Table 14. Cell 0 is the LSB (closest to TDO).
Table 14. JTAG Instruction Register
The first line shows the cells in the IR that capture from
a parallel input in the capture-IR controller state. The
second line shows the cells that always load a logic 1 in
the capture-IR controller state. The third line shows the
cells that always load a logic 0 in the capture-IR control-
ler state. Cell 3 (MSB of IR) is tied to status signal PINT,
and cell 2 is tied to status signal JINT. The state of these
signals can therefore be captured during capture-IR and
shifted out during SHIFT-IR controller states.
34
parallel input?
always logic 1?
always logic 0?
IR Cell #:
N
N
Y
3
N
N
Y
2
(continued)
N
N
Y
1
N
N
Y
0
Boundary-Scan Register
All of the chip's inputs and outputs are incorporated in a
JTAG scan path shown in Table 15. The types of
boundary-scan cells are as follows:
I = input cell
O = 3-state output cell
B = bidirectional (I/O) cell
OE = 3-state control cell
DC = bidirectional control cell
Lucent Technologies Inc.
February 1997