ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 38

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
4 Hardware Architecture
4.13 Clock Synthesis
The DSP1628 provides an on-chip, programmable
clock synthesizer. Figure 10 is the clock source dia-
gram. The 1X CKI input clock, the output of the synthe-
sizer, or a slow internal ring oscillator can be used as
the source for the internal DSP clock. The clock synthe-
sizer is based on a phase-locked loop (PLL), and the
terms clock synthesizer and PLL are used interchange-
ably.
On powerup, CKI is used as the clock source for the
DSP. This clock is used to generate the internal proces-
sor clocks and CKO, where f
propriate bits in the pllc control register (described in
Table 36) will enable the clock synthesizer to become
the clock source. The powerc register, which is dis-
cussed in Section 4.14, can override the selection to
stop clocks or force the use of the slow clock for low-
power operation.
36
CKI INPUT CLOCK
f
CKI
PLL/SYNTHESIZER
Nbits[2:0]
N
DETECTOR
PHASE
CKI
= f
(continued)
CKO
Mbits[4:0]
OSCILLATOR
Figure 10. Clock Source Block Diagram
. Setting the ap-
RING
M
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
LOCK
CHARGE
PUMP
FILTER
LOOP
LF[3:0]
PLL Control Signals
The input to the PLL comes from one of the three mask-
programmable clock options: CMOS, or small-signal.
The PLL cannot operate without an external input clock.
To use the PLL, the PLL must first be allowed to stabi-
lize and lock to the programmed frequency. After the
PLL has locked, the LOCK flag is set and the lock detect
circuitry is disabled. The synthesizer can then be used
as the clock source. Setting the PLLSEL bit in the pllc
register will switch sources from f
glitching. It is important to note that the setting of the
pllc register must be maintained. Otherwise, the PLL
will seek the new set point. Every time the pllc register
is written, the LOCK flag is reset.
powerc
VCO
VCO CLOCK
f
VCO
f
PLLEN
SLOW CLOCK
Preliminary Data Sheet
SLOWCKI
2
f
CKI
Lucent Technologies Inc.
CKI
5-4520 (F)
M
U
X
February 1997
to f
PLLSEL
f
INTERNAL CLOCK
PROCESSOR
VCO
INTERNAL
pllc
CLOCK
/2 without