ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 73

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
5 Software Architecture
N Field
Number of instructions to be loaded into the cache. Zero
implies redo operation.
K Field
Number of times the N instructions in cache are to be
executed. Zero specifies use of value in cloop register.
JA Field
12-bit jump address.
R/W Field
A zero specifies a write, *(OFFSET) = DR.
A one specifies a read, DR = *(OFFSET).
Table 60. F3 Field
Specifies the operation in an F3 ALU instruction.
Table 61. SRC2 Field
Specifies operands in an F3 ALU instruction.
Lucent Technologies Inc.
1000
1001
1010
1011
1101
1110
1111
F3
SRC2
00
10
01
11
aD = aS[h, l]
aD = aS[h, l]
aS[h, l]
aS[h, l]
aD = aS[h, l]
aD = aS[h, l]
aD = aS[h, l]
Operation
Operands
aSh, IM16
aSl, IM16
aS, aT
aS, p
&
–
+
&
–
^
|
(continued)
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
Table 62. BMU Encodings
Note: xx encodes the auxiliary register to be used; 00 (ar0),
0000
0001
0000
0001
1000
1001
1000
1001
1100
1101
1100
1101
0000
0001
1110
0010
1110
0010
1110
1010
0111
0111
F4
01(ar1), 10 (ar2), or 11(ar3).
DSP1628 Digital Signal Processor
00xx
00xx
10xx
10xx
0000
0000
1000
1000
0000
0000
1000
1000
1100
11xx
0000
00xx
0100
01xx
1000
10xx
0000
0001
AR
aD = aS >> arM
aD = aS << arM
aD = aS >>> arM
aD = aS <<< arM
aD = aS >> aS
aD = aS << aS
aD = aS >>> aS
aD = aS <<< aS
aD = aS >> IM16
aD = aS << IM16
aD = aS >>> IM16
aD = aS <<< IM16
aD = exp(aS)
aD = norm(aS, arM)
aD = extracts(aS, IM16)
aD = extracts(aS, arM)
aD = extractz(aS, IM16)
aD = extractz(aS, arM)
aD = insert(aS, IM16)
aD = insert(aS, arM)
aD = aS:aa0
aD = aS:aa1
Operation
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