tn28f010-90 Intel Corporation, tn28f010-90 Datasheet - Page 8

• Manufacturer Part Number: tn28f010-90
• Description: 1024k 128k X 8 Cmos Flash Memory
• Manufacturer: Intel Corporation

28F010
With CE
to high voltage V
vates the operation Data read from locations 0000H
and 0001H represent the manufacturer’s code and
the device code respectively
The manufacturer- and device-codes can also be
read via the command register for instances where
the 28F010 is erased and reprogrammed in the tar-
get system Following a write of 90H to the com-
mand register a read from address location 0000H
outputs the manufacturer code (89H) A read from
address 0001H outputs the device code (B4H)
Write
Device erasure and programming are accomplished
via the command register when high voltage is ap-
plied to the V
serve as input to the internal state-machine The
state-machine outputs dictate the function of the
device
The command register itself does not occupy an ad-
dressable memory location The register is a latch
NOTES
1 Bus operations are defined in Table 2
2 IA
3 ID
4 Following the Read int e ligent ID command two read operations access manufacturer and device codes
5 Figure 6 illustrates the Quick Erase Algorithm
6 Figure 5 illustrates the Quick Pulse Programming Algorithm
7 The second bus cycle must be followed by the desired command register write
8
Read Memory
Read Intelligent Identifier
Codes
Set-up Erase Erase
Erase Verify
Set-up Program Program
Program Verify
Reset
EA
PA
Addresses are latched on the falling edge of the WE
EVD
PD
PVD
e
e
e
e
e
(7)
(4)
e
e
Identifier address 00H for manufacturer code 01H for device code
Identifier Data Data read from location IA during device identification (Mfr
Erase Address Address of memory location to be read during erase verify
Program Address Address of memory location to be programmed
Command
Program Data Data to be programmed at location PA Data is latched on the rising edge of WE
Erase Verify Data Data read from location EA during erase verify
Program Verify Data Data read from location PA during program verify PA is latched on the Program command
and OE
(5)
PP
(6)
pin The contents of the register
ID
(5)
(see DC Characteristics) acti-
at a logic low level raising A9
(6)
Cycles
Req’d
Bus
1
3
2
2
2
2
2
Operation
Table 3 Command Definitions
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
(1)
pulse
Address
EA
used to store the command along with address and
data information needed to execute the command
The command register is written by bringing WE
a logic-low level (V
are latched on the falling edge of WE
latched on the rising edge of the WE
dard microprocessor write timings are used
Refer to AC Write Characteristics and the Erase
Programming
parameters
COMMAND DEFINITIONS
When low voltage is applied to the V
tents of the command register default to 00H en-
abling read-only operations
Placing high voltage on the V
write operations Device operations are selected by
writing specific data patterns into the command reg-
ister
commands
IA
X
X
X
X
X
(2)
Table 3 defines these 28F010 register
Data
A0H
C0H
FFH
00H
90H
20H
40H
(3)
Waveforms
e
Operation
IL
89H Device
) while CE
Read
Write
Read
Write
Read
Write
Second Bus Cycle
(1)
for
PP
e
Address
B4H)
pin enables read
is low Addresses
specific
PA
IA
X
X
X
X
PP
pin the con-
while data is
pulse Stan-
(2)
Data
EVD
PVD
FFH
20H
timing
PD
ID
(3)
to