tn28f010-90 Intel Corporation, tn28f010-90 Datasheet - Page 12

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tn28f010-90

Manufacturer Part Number
tn28f010-90
Description
1024k 128k X 8 Cmos Flash Memory
Manufacturer
Intel Corporation
Datasheet

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28F010
12
1 See DC Characteristics for the value of V
V
2 Erase Verify is performed only after chip-erasure A
final read compare may be performed (optional) after
the register is written with the read command
PPL
Figure 6 28F010 Quick Erase Algorithm
290207 – 6
PPH
and
Operation
Standby
Write
Write
Standby
Write
Standby
Read
Standby
Write
Standby
3 Refer to principles of operation
4 CAUTION The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice
Bus
Command
Set-up
Erase
Erase
Erase
Verify
Read
(2)
Entire Memory Must
Before Erasure
Use Quick Pulse
Programming Algorithm
(Figure 5)
Wait for V
Initialize Addresses and
Pulse-Count
Data
Data
Duration of Erase Operation
(t
Addr
Data
Operation
t
Read Byte to Verify Erasure
Compare Output to FFH
Increment Pulse-Count
Data
Register for Read Operations
Wait for V
WHGL
WHWH2
e
e
e
e
e
20H
20H
Byte to Verify
A0H Stops Erase
00H Resets the
)
Comments
PP
PP
(3)
Ramp to V
Ramp to V
e
PPH
PPL
00H
(1)
(1)

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