tn28f010-90 Intel Corporation, tn28f010-90 Datasheet - Page 13

• Manufacturer Part Number: tn28f010-90
• Description: 1024k 128k X 8 Cmos Flash Memory
• Manufacturer: Intel Corporation

DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory ar-
rays Intel provides two read-control inputs to ac-
commodate multiple memory connections Two-line
control provides for
a the lowest possible memory power dissipation
b complete assurance that output bus contention
To efficiently use these two control inputs an ad-
dress-decoder output should drive chip-enable
while the system’s read signal controls all flash-
memories and other parallel memories This assures
that only enabled memory devices have active out-
puts while deselected devices maintain the low
power standby condition
Power Supply Decoupling
Flash-memory power-switching characteristics re-
quire careful device decoupling System designers
are interested in three supply current (I
standby active and transient current peaks pro-
duced by falling and rising edges of chip-enable The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks
Each device should have a 0 1 mF ceramic capacitor
connected between V
and V
Place the high-frequency low-inherent-inductance
capacitors as close as possible to the devices Also
for every eight devices a 4 7 mF electrolytic capaci-
tor should be placed at the array’s power supply
connection between V
tor will overcome voltage slumps caused by printed-
NOTES
1 Formula to calculate typical Program Program Verify Power
typical
typical
2 Formula to calculate typical Erase Erase Verify Power
3 One Complete Cycle
4 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples from production lots
Bytes)
and
will not occur
SS
a
Array Program Program Verify
Array Erase Erase Verify
One Complete Cycle
t
a
WHGL c
V
CC
(I
I
CC3
Operation
PP4
e
CC
typical
typical)
CC
Array Preprogram
and V
and V
Table 4 28F010 Typical Update Power Dissipation
c
a
t
SS
ERASE
SS
V
and between V
CC c
The bulk capaci-
typical
CC
a
) issues
Array Erase
Bytes
a
I
CC5
c
PP
e
typical
typical
V
a
e
PP
Program
Notes
circuit-board trace inductance
charge to the smaller capacitors as needed
V
Programming flash-memories while they reside in
the target system requires that the printed circuit
board designer pay attention to the V
ply trace The V
rent for programming Use similar trace widths and
layout considerations given the V
equate V
crease V
Power Up Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions Upon power-up the 28F010 is indifferent
as to which power supply V
first Power supply sequencing is not required Inter-
nal circuitry in the 28F010 ensures that the com-
mand register is reset to the read mode on power
up
A system designer must guard against active writes
for V
Since both WE
mand write driving either to V
The control register architecture provides an added
level of protection since alteration of memory con-
tents only occurs after successful completion of the
two-step command sequences
28F010 Power Dissipation
When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off Table 4 illustrates the
power dissipated when updating the 28F010
c
(V
V
PP
1
2
3
PP c
PP3
t
Prog Pulses (t
WHGL c
CC
Trace on Printed Circuit Boards
typical
voltages above V
PP
PP
Bytes
voltage spikes and overshoots
c
supply traces and decoupling will de-
Bytes)
t
c
WHWH1 c
PP
ERASE
and CE
typical
pin supplies the memory cell cur-
typical
(4)
Power Dissipation
(Watt-Seconds)
I
CC2
Prog Pulses (t
LKO
must be low for a com-
a
PP
typical
0 171
0 136
0 478
I
PP5
when V
IH
or V
CC
will inhibit writes
and will supply
typical
a
power bus Ad-
CC
PP
WHWH1 c
t
PP
WHGL c
power sup-
powers up
c
is active
28F010
t
WHGL c
I
I
CC4
PP2
13