AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 78

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9517-0
APPLICATION NOTES
USING THE AD9517 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
where:
f
t
Figure 68 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
See the AN-756 application note and the AN-501 application note
at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9517 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
A
J
is the rms jitter on the sampling clock.
is the highest analog frequency being digitized.
110
100
90
80
70
60
50
40
30
SNR
10
(dB)
Figure 68. SNR and ENOB vs. Analog Input Frequency
=
20
×
log
⎛
⎜
⎜
⎝
2
π
f
f
1
A
A
t
100
(MHz)
J
⎞
⎟
⎟
⎠
SNR = 20log
2πf
1
A
t
J
1k
18
16
14
12
10
8
6
Rev. 0 | Page 78 of 80
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9517 provide the lowest jitter
clock signals available from the AD9517. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 57 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
is recommended, as shown in Figure 69. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the switching threshold (V
LVDS CLOCK DISTRIBUTION
The AD9517 provides four clock outputs (OUT4 to OUT7) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV output
swing across a 100 Ω resistor. The LVDS output meets or
exceeds all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 71.
See the AN-586 application note at www.analog.com for more
information on LVDS.
VS_LVPECL
VS_LVPECL
LVPECL
VS
LVDS
LVPECL
200Ω
Figure 70. LVPECL with Parallel Transmission Line
Figure 69. LVPECL Far-End Thevenin Termination
Figure 71. LVDS Output Termination
DIFFERENTIAL (COUPLED)
0.1nF
0.1nF
V
(NOT COUPLED)
200Ω
SINGLE-ENDED
T
= V
S
TRANSMISSION LINE
100Ω DIFFERENTIAL
50Ω
50Ω
– 1.3V
100Ω
S
− 1.3 V).
(COUPLED)
127Ω
83Ω
VS_LVPECL
100Ω
100Ω
127Ω
83Ω
VS_LVPECL
LVPECL
V
VS
LVDS
S
LVPECL