AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 75

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
197
197
198
198
Reg.
Addr
(Hex) Bit(s)
199
199
19A
19A
19B
19B
19C
19C
19C
19C
19C
19C
19D
19E
19E
19F
Table 58. LVDS/CMOS Channel Dividers
<4>
<3:0> Divider 1 Phase Offset
<1>
<0>
<7:4> Low Cycles Divider 2.1
<3:0> High Cycles Divider 2.1
<7:4> Phase Offset Divider 2.2
<3:0> Phase Offset Divider 2.1
<7:4> Low Cycles Divider 2.2
<3:0> High Cycles Divider 2.2
<5>
<4>
<3>
<2>
<1>
<0>
<0>
<7:4> Low Cycles Divider 3.1
<3:0> High Cycles Divider 3.1
<7:4> Phase Offset Divider 3.2
Divider 1 Start High
Divider 1 Direct to Output
Divider 1 DCCOFF
Name
Bypass Divider 2.2
Bypass Divider 2.1
Divider 2 Nosync
Divider 2 Force High
Start High Divider 2.2
Start High Divider 2.1
Divider 2 DCCOFF
Description
Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
Phase offset.
Connect OUT2 and OUT3 to Divider 2 or directly to VCO or CLK.
<1> = 0; OUT2 and OUT3 are connected to Divider 1.
<1> = 1:
If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT2 and OUT3.
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT2 and OUT3.
If 0x1E1<1:0> = 01b, there is no effect.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Description
Number of clock cycles of 2.1 divider input during which 2.1 output stays low.
Number of clock cycles of 2.1 divider input during which 2.1 output stays high.
Refer to LVDSCMOS channel divider function description.
Refer to LVDSCMOS channel divider function description.
Number of clock cycles of 2.2 divider input during which 2.2 output stays low.
Number of clock cycles of 2.2 divider input during which 2.2 output stays high.
Bypass (and power-down) 2.2 divider logic, route clock to 2.2 output.
<5> = 0; do not bypass.
<5> = 1; bypass.
Bypass (and power-down) 2.1 divider logic, route clock to 2.1 output.
<4> = 0; do not bypass.
<4> = 1; bypass.
Nosync.
<3> = 0; obey chip-level SYNC signal.
<3> = 1; ignore chip-level SYNC signal.
Force Divider 2 output high. Requires that nosync also be set.
<2> = 0; force low.
<2> = 1; force high.
Divider 2.2 start high/low.
<1> = 0; start low.
<1> = 1; start high.
Divider 2.1 start high/low.
<0> = 0; start low.
<0> = 1; start high.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Number of clock cycles of divider 3.1 input during which 3.1 output stays low.
Number of clock cycles of 3.1 divider input during which 3.1 output stays high.
Refer to LVDSCMOS channel divider function description.
Rev. 0 | Page 75 of 80
AD9517-0