AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 45

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Duty Cycle and Duty-Cycle Correction (Divider 2 and
Divider 3)
The same duty cycle and DCC considerations apply to Divider 2
and Divider 3 as to Divider 0 and Divider 1 (see Duty Cycle and
Duty-Cycle Correction (0, 1)); however, with these channel
dividers, the number of possible configurations is even more
complex.
Duty-cycle correction on Divider 2 and Divider 3 requires the
following channel divider conditions:
• An even D
• An odd D
• If only one divider is bypassed, it must be the second
• If only one divider has an even divide-by, it must be the
The possibilities for the duty cycle of the output clock from
Divider 2 and Divider 3 are shown in Table 40 through Table 44
Table 40. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd
cycles).
low cycles must be one greater than the number of high cycles).
divider, X.2.
second divider, X.2.
N
1
1
1
Even, Odd
Even, Odd
Even, Odd
Even, Odd
X.Y
X.1
X.Y
must be set as M
+ M
must be set as M
D
X.1
X.1
+ 2
1
1
1
1
Even, Odd
Even, Odd
N
1
X.2
X.Y
+ M
X.Y
D
= N
X.2
= N
X.2
+ 2
X.Y
X.Y
+ 1 (the number of
(low cycles = high
Output Duty Cycle
50%
33.3%
40%
(N
(N
(N
(N
(N
(N
(N
(N
X.1
X.1
X.1
X.1
X.2
X.2
X.2
X.2
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
X.1
X.1
X.2
X.2
+ 2)
+ 2)
+ 2)
+ 2)
Rev. 0 | Page 45 of 80
Table 41. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
Duty Cycle
50%
X%
50%
X%
50%
X%
Table 42. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
Divider
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
N
1
1
Even (N
Even (N
Odd (M
Odd (M
Even (N
Even (N
Odd (M
Odd (M
Odd (M
Odd (M
X.1
+ M
N
1
1
Even, Odd
Even, Odd
Even, Odd
Even, Odd
X.1
X.1
X.1
X.1
X.1
X.1
X.1
D
X.1
X.1
X.1
X.1
X.1
+ M
X.1
= N
= N
= N
= N
= N
= N
D
= M
= M
= M
= M
+ 2
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 2
)
)
)
)
N
1
1
1
1
1
1
Even (N
Even (N
Even (N
Even (N
Odd (M
Odd (M
N
1
1
1
1
Even, Odd
Even, Odd
X.2
X.2
+ M
+ M
D
X.2
X.2
X.2
D
X.2
X.2
X.2
X.2
X.2
X.2
X.2
= N
= N
= M
= M
= M
= M
+ 2
+ 2
X.2
X.2
X.2
X.2
X.2
X.2
+ 1)
+ 1)
)
)
)
)
AD9517-0
Output
Duty Cycle
50%
X%
(N
(N
(N
(N
(N
(N
(N
(N
X.1
X.1
X.1
X.1
X.2
X.2
X.2
X.2
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
Output
Duty Cycle
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
X.1
X.1
X.2
X.2
+ 2)
+ 2)
+ 2)
+ 2)