AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 10

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9517-0
Parameter
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 2.55 GHz; OUTPUT = 2.55 GHz
VCO = 2.95 GHz; LVPECL = 491.52 MHz; PLL LBW = 75 kHz
VCO = 2.95 GHz; LVPECL = 122.88 MHz; PLL LBW = 75 kHz
VCO = 2.70 GHz; LVPECL = 122.88 MHz; PLL LBW = 187 kHz
VCO = 2.70 GHz; LVPECL = 61.44 MHz; PLL LBW = 187 kHz
VCO = 2.58 GHz; LVPECL = 61.44 MHz; PLL LBW = 75 kHz
VCO = 2.80 GHz; LVPECL = 155.52 MHz; PLL LBW = 12.8 kHz
VCO = 2.95 GHz; LVPECL = 77.76 MHz; PLL LBW = 12.8 kHz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
Min
Typ
54
77
109
79
114
163
Rev. 0 | Page 10 of 80
Typ
−51
−80
−106
−125
−142
−146
Max
Min
Min
Unit
f
f
f
f
f
f
Max
S
S
S
S
S
S
Typ
513
544
rms
rms
rms
rms
rms
rms
Typ
148
342
212
320
184
304
221
345
210
334
Max
Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Max
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unit
f
f
S
S
Unit
f
f
f
f
f
f
f
f
f
f
S
S
S
S
S
S
S
S
S
S
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
Test Conditions/Comments
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 19.44 MHz; R = 1
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz