AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 6

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9517-0
Parameter
PLL DIGITAL LOCK DETECT WINDOW
1
2
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
1
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
LVDS CLOCK OUTPUTS
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V
OUT4, OUT5, OUT6, OUT7
OUT0, OUT1, OUT2, OUT3
Required to Lock (Coincidence of Edges)
To Unlock After Lock (Hysteresis)
Input Frequency
Input Sensitivity, Differential
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Input Level, Differential
Input Common-Mode Voltage, V
Output Frequency, Maximum
Output High Voltage (V
Output Low Voltage (V
Output Differential Voltage (V
Output Frequency
Differential Output Voltage (V
Delta V
Output Offset Voltage (V
Delta V
Short-Circuit Current (I
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
OD
OS
SA
OL
OH
, I
)
OS
)
SB
)
)
OD
OD
CMR
CM
2
)
)
2
Min
0
0
1.3
1.3
3.9
1
Min
1
Min
2950
V
V
550
247
1.125
S
S
− 1.12
− 2.03
Typ
150
1.57
150
4.7
2
Typ
3.5
7.5
3.5
7
15
11
Max
2.4
1.6
2
1.8
1.8
5.7
Rev. 0 | Page 6 of 80
Typ
V
V
790
360
1.24
14
S
S
Max
− 0.98
− 1.77
Unit
GHz
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
CM
.
Max
980
800
454
24
V
V
25
1.375
25
Unit
ns
ns
ns
ns
ns
ns
S
S
− 0.84
− 1.49
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Test Conditions/Comments
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by 0x17<1:0> and 0x18<4>
0x17<1:0> = 00b, 01b,11b; 0x18<4> = 1b
0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b
0x17<1:0> = 10b; 0x18<4> = 0b
0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b
0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b
0x17<1:0> = 10b; 0x18<4> = 0b
Unit
MHz
V
V
mV
MHz
mV
mV
V
mV
mA
Test Conditions/Comments
Termination = 50 Ω to V
Differential (OUT, OUT)
Using direct to output; see Figure 25
Differential termination 100 Ω @ 3.5 mA
Differential (OUT, OUT)
See Figure 26
Output shorted to GND
S
− 2 V