AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 67

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
1D
1D
1D
1D
1F
1F
1F
1F
1F
1F
1F
<3>
<2>
<1>
<0>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
LD Pin
Comparator
Enable
Holdover
Enable
External
Holdover
Control
Holdover
Enable
VCO Cal
Finished
Holdover
Active
REF2
Selected
VCO
Frequency >
Threshold
REF2
Frequency >
Threshold
REF1
Frequency >
Threshold
Digital Lock Readback register: digital lock detect.
Detect
Description
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When in the internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to
determine if the PLL was previously in a locked state (see Figure 51). Otherwise, this can be used with
the REFMON and STATUS pins to monitor the voltage on this pin.
<3> = 0; disable LD pin comparator; internal/automatic holdover controller treats this pin as true (high).
<3> = 1; enable LD pin comparator.
Along with <0> enables the holdover function.
<2> = 0; holdover disabled.
<2> = 1; holdover enabled.
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
<1> = 0; automatic holdover mode—holdover controlled by automatic holdover circuit.
<1> = 1; external holdover mode—holdover controlled by SYNC pin.
Along with <2> enables the holdover function.
<0> = 0; holdover disabled.
<0> = 1; holdover enabled.
Readback register: status of the VCO calibration.
<6> = 0; VCO calibration not finished.
<6> = 1; VCO calibration finished.
Readback register: indicates if the part is in the holdover state (see Figure 51). This is not the same as holdover
enabled.
<5> = 0; not in holdover.
<5> = 1; holdover state active.
Readback register: indicates which PLL reference is selected as the input to the PLL.
<4> = 0; REF1 selected (or differential reference if in differential mode).
<4> = 1; REF2 selected.
Readback register: indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and VCO
Frequency Status Monitor).
<3> = 0; VCO frequency is less than the threshold.
<3> = 1; VCO frequency is greater than the threshold.
Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x1A<6>.
<2> = 0; REF2 frequency is less than threshold frequency.
<2> = 1; REF2 frequency is greater than threshold frequency.
Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x1A<6>.
<1> = 0; REF1 frequency is less than threshold frequency.
<1> = 1; REF1 frequency is greater than threshold frequency.
<0> = 0; PLL is not locked.
<0> = 1; PLL is locked.
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AD9517-0