MT18LSDT6472 Micron, MT18LSDT6472 Datasheet - Page 9

• Manufacturer Part Number: MT18LSDT6472
• Description: 168-Pin SDRAM DIMMs (x72) ECC
• Manufacturer: Micron

16, 32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
SD18C16_32_64x72G_B.p65 – Pub. 11/01
CAS Latency
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in the CAS Latency Diagram. The CAS Latency
Table indicate the operating frequencies at which each
CAS latency setting can be used.
operation or incompatibility with future versions
may result.
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
CLK
CLK
DQ
DQ
CAS LATENCY DIAGRAM
READ
READ
T0
T0
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
T2
NOP
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
9
168-PIN REGISTERED SDRAM DIMM
128MB / 256MB / 512MB (x72, ECC)
Operating Mode
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
*Input register will add an extra clock cycle when in registered
SPEED
mode.
-13E
-133
-10E
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATENCY = 2*
CAS LATENCY TABLE
ALLOWABLE OPERATING
CAS
133
100
100
FREQUENCY (MHz)
LATENCY = 3*
©2001, Micron Technology, Inc.
CAS
NA
143
133