MT18LSDT6472 Micron, MT18LSDT6472 Datasheet - Page 4

• Manufacturer Part Number: MT18LSDT6472
• Description: 168-Pin SDRAM DIMMs (x72) ECC
• Manufacturer: Micron

PIN DESCRIPTIONS
NOTE: Pin numbers are listed in module pinout order and do not necessarily correlate with symbols.
16, 32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
SD18C16_32_64x72G_B.p65 – Pub. 11/01
117–121, 123, 126
112-113, 130-131
42, 79, 125, 163
PIN NUMBERS
28-29, 46-47,
27, 111, 115
(512MB)
165-167
39, 122
33–38,
30, 45
128
147
81
83
WE#, CAS#,
BA0, BA1
SYMBOL
CK0-CK3
DQMB0-
SA0-SA2
S0#, S2#
(512MB)
(128MB/
DQMB7
A0-A11
256MB)
A0-A12
RAS#
REGE
CKE0
SCL
WP
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE
Command Inputs: WE#, CAS#, and RAS# (along with
S0#, S2#) define the command being entered.
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1-CK3 are terminated.
Clock Enable: CKE0 activates (HIGH) and deactivates
(LOW) the CK0 signal. Deactivating the clock provides
POWER-DOWN and SELF REFRESH operation (all device
banks idle) or CLOCK SUSPEND operation (burst access in
progress). CKE0 is synchronous except after the device
enters power-down and self refresh modes, where CKE0
becomes asynchronous until after exiting the same
mode. The input buffers, including CK0, are disabled
during power-down and self refresh modes, providing
low standby power.
Chip Select: S0#, S2# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S0#, S2# are registered HIGH. S0#, S2# are
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
Address Inputs: A0-A11 (128MB/256MB) or A0-A12
(512MB) are sampled during the ACTIVE command
(device row-address A0-A11/12) and READ/WRITE
command (device column-address A0-A9 (128MB) or A0-
A9/A11 (256MB/512MB), with A10 defining auto
precharge) to select one location out of the memory
array in the respective device bank. A10 is sampled
during a PRECHARGE command to determine if both
device banks are to precharged (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE
REGISTER command.
Write Protect: Serial presence-detect hardware write protect.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Register Enable.
4
168-PIN REGISTERED SDRAM DIMM
128MB / 256MB / 512MB (x72, ECC)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2001, Micron Technology, Inc.