MT18LSDT6472 Micron, MT18LSDT6472 Datasheet - Page 7

• Manufacturer Part Number: MT18LSDT6472
• Description: 168-Pin SDRAM DIMMs (x72) ECC
• Manufacturer: Micron

Mode Register Definition
MODE REGISTER
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in Mode Register Definition Diagram. The mode
register is programmed via the LOAD MODE REGIS-
TER command and will retain the stored information
until it is programmed again or the device loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
For the 512MB module, address A12 (M12) is unde-
fined but should be driven LOW during loading of the
mode register.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
16, 32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
SD18C16_32_64x72G_B.p65 – Pub. 11/01
The mode register is used to define the specific mode
Mode register bits M0-M2 specify the burst length,
The mode register must be loaded when all device
7
168-PIN REGISTERED SDRAM DIMM
128MB / 256MB / 512MB (x72, ECC)
Burst Length
oriented, with the burst length being programmable,
as shown in Mode Register Definition Diagram. The
burst length determines the maximum number of col-
umn locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached, as shown in the Burst Defini-
tion Table. The block is uniquely selected by A1-A9
(64MB) or A1-A9, A11 (128MB/256MB) when the burst
length is set to two; A2-A9 or A2-A9, A11 when the burst
length is set to four; and by A3-A9 or A3-A9, A11 when
the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached, as shown in
the Burst Definition Table.
Read and write accesses to the SDRAM are burst
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.