MT18LSDT6472 Micron, MT18LSDT6472 Datasheet - Page 2

• Manufacturer Part Number: MT18LSDT6472
• Description: 168-Pin SDRAM DIMMs (x72) ECC
• Manufacturer: Micron

PART NUMBERS
NOTE: The designators for component and PCB revision are
16, 32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
SD18C16_32_64x72G_B.p65 – Pub. 11/01
GENERAL DESCRIPTION
MT18LSDT6472G are high-speed CMOS, dynamic ran-
dom-access, 128MB, 256MB, and 512MB memory mod-
ules organized in a x72 (ECC) configuration. These mod-
ules use internally configured quad-bank SDRAM de-
vices, with a synchronous interface (all signals are regis-
tered on the positive edge of clock signal CK0).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used to
select the device bank and row to be accessed (BA0, BA1
select the device bank, A0-A11 select the device row for
the 128MB and 256MB modules; A0-A12 select the de-
vice row for the 512MB module). The address bits regis-
tered coincident with the READ or WRITE command are
used to select the starting device column location for the
burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or full page,
with a burst terminate option. An auto precharge func-
tion may be enabled to provide a self-timed device row
precharge that is initiated at the end of the burst se-
quence.
PART NUMBER
MT18LSDT1672G-13E__
MT18LSDT1672G-133__
MT18LSDT1672G-10E__
MT18LSDT3272G-133__
MT18LSDT3272G-13E__
MT18LSDT3272G-10E__
MT18LSDT6472G-133__
MT18LSDT6472G-13E__
MT18LSDT6472G-10E__
The MT18LSDT1672G, MT18LSDT3272G, and
Read and write accesses to the SDRAM modules are
These modules provide for programmable READ or
the last two characters of each part number. Consult
factory for current revision codes. Example:
MT18LSDT1672G-133B1
CONFIGURATION SYSTEM BUS SPEED
16 Meg x 72
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
133 MHz
133 MHz
100 MHz
133 MHz
133 MHz
100 MHz
133 MHz
133 MHz
100 MHz
2
168-PIN REGISTERED SDRAM DIMM
128MB / 256MB / 512MB (x72, ECC)
ture. Precharging one device bank while accessing one
of the other three device banks will hide the PRECHARGE
cycles and provide seamless, high-speed, random-ac-
cess operation.
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
operating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
device column-address generation, the ability to inter-
leave between device banks in order to hide precharge
time, and the capability to randomly change device col-
umn addresses on each clock cycle during a burst ac-
cess. For more information regarding SDRAM opera-
tion, refer to the 64Mb, 128Mb, and 256Mb SDRAM data
sheets.
PLL AND REGISTER OPERATION
mode (REGE pin HIGH), where the control/address in-
put signals are latched in the register on one rising clock
edge and sent to the SDRAM devices on the following
rising clock edge (data access is delayed by one clock), or
in buffered mode (REGE pin LOW) where the input sig-
nals pass through the register/buffer to the SDRAM de-
vices on the same clock. A phase-lock loop (PLL) on the
modules is used to redrive the clock signals to the SDRAM
devices to minimize system clock loading (CK0 is con-
nected to the PLL, and CK1, CK2, and CK3 are termi-
nated).
SERIAL PRESENCE-DETECT OPERATION
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM’s
SCL (clock) and SDA (data) signals, together with SA(2:0),
which provide eight unique DIMM/EEPROM addresses.
These modules use an internal pipelined architec-
These modules are designed to operate in 3.3V, low-
SDRAM modules offer substantial advances in DRAM
These modules can be operated in either registered
These modules incorporate serial presence-detect
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.