MT18LSDT6472 Micron, MT18LSDT6472 Datasheet - Page 6

• Manufacturer Part Number: MT18LSDT6472
• Description: 168-Pin SDRAM DIMMs (x72) ECC
• Manufacturer: Micron

SDRAM COMPONENT DESCRIPTION
memory devices used for these modules are quad-
bank DRAMs, that operate at 3.3V and include a syn-
chronous interface (all signals are registered on the
positive edge of the clock signal, CK). The four banks of
a x4, 64Mb device are each configured as 4,096 bit-
rows, by 1,024 bit-columns, by 4 input/output bits.
The four banks of a x4, 128Mb device are each config-
ured as 4,096 bit-rows, by 2,048 bit-columns, by 4 in-
put/output bits. The four banks of a x4, 256MB device
are configured as 8,192 bit-rows, by 2,048 bit columns,
by 4 input/output bits.
MODULE FUNCTIONAL DESCRIPTION
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed BA0
and BA1 select the device bank, A0-A11 (for 128MB and
256MB module), or A0-A12 (for 512MB module), select
the device row. The address bits A0-A9 (for 64MB) or
A0-A9, A11 (for the 256MB and 512MB module), regis-
tered coincident with the READ or WRITE command
are used to select the starting device column location
for the burst access.
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
16, 32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
SD18C16_32_64x72G_B.p65 – Pub. 11/01
In general, the 64Mb, 128Mb, and 256Mb SDRAM
Read and write accesses to the SDRAM are burst
Prior to normal operation, the SDRAM must be ini-
6
168-PIN REGISTERED SDRAM DIMM
128MB / 256MB / 512MB (x72, ECC)
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this
100µs period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
COMMAND INHIBIT or NOP command having been ap-
plied, a PRECHARGE command should be applied. All de-
vice banks must then be precharged, thereby placing the
device in the all device banks idle state.
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
SDRAMs must be powered up and initialized in a
Once the 100µs delay has been satisfied with at least one
Once in the idle state, two AUTO REFRESH cycles
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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©2001, Micron Technology, Inc.
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