LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 90
LM3S300
Manufacturer Part Number
LM3S300
Description
Lm3s300 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S300.pdf
(380 pages)
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Reset
Reset
Type
Type
System Control
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
90
Bit/Field
31:27
23:19
26
25
24
RO
RO
31
15
0
0
reserved
RO
RO
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
30
14
0
0
reserved
RO
RO
29
13
reserved
reserved
0
0
COMP2
COMP1
COMP0
Name
I2C0
R/W
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
RO
COMP2
R/W
RO
26
10
0
0
COMP1
R/W
RO
Reset
25
0
9
0
0
0
0
0
0
reserved
COMP0
Preliminary
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
SSI0
R/W
RO
20
0
4
0
RO
RO
19
0
3
0
reserved
TIMER2
R/W
RO
18
0
2
0
TIMER1
UART1
R/W
R/W
17
0
1
0
June 04, 2008
TIMER0
UART0
R/W
R/W
16
0
0
0
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