LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 296

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Inter-Integrated Circuit (I
13.2.1.5 Arbitration
13.2.2
296
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
Available Speed Modes
The I
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I
page 313).
The I
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 13-1 on page 296 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 13-1. Examples of I
System Clock
12.5 Mhz
16.7 Mhz
20 Mhz
25 Mhz
4 Mhz
6 Mhz
2
2
C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
C clock period is calculated as follows:
2
C) Interface
Timer Period
0x0C
0x01
0x02
0x06
0x08
0x09
Standard Mode
2
C Master Timer Period versus Speed Mode
96.2 Kbps
100 Kbps
100 Kbps
100 Kbps
89 Kbps
93 Kbps
Preliminary
Timer Period
0x01
0x02
0x02
0x03
-
-
2
C Master Timer Period (I2CMTPR) register (see
Fast Mode
312 Kbps
278 Kbps
333 Kbps
312 Kbps
-
-
June 04, 2008