LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 162

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Timers
9.2.3.2
162
Table 9-2. 16-Bit Timer With Prescaler Configurations
a. Tc is the clock period.
16-Bit Input Edge Count Mode
Note:
Note:
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 9-2 on page 163 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
00000000
00000001
00000010
Prescale
11111100
------------
11111110
11111111
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
The prescaler is not available in 16-Bit Input Edge Count mode.
#Clock (T c)
254
255
256
1
2
3
--
a
Max Time
665.8458
668.4672
671.0886
2.6214
5.2428
7.8642
--
Units
mS
mS
mS
mS
mS
mS
--
Preliminary
June 04, 2008