LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 13

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

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Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 217
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Synchronous Serial Interface (SSI) ............................................................................................ 256
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June 04, 2008
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 198
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 199
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 200
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 201
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 202
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 203
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 204
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 205
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 206
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 207
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 208
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 209
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 210
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 211
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 212
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 213
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 214
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 215
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 216
UART Data (UARTDR), offset 0x000 ............................................................................... 224
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 226
UART Flag (UARTFR), offset 0x018 ................................................................................ 228
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 230
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 231
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 232
UART Control (UARTCTL), offset 0x030 ......................................................................... 234
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 236
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 238
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 240
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 241
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 242
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 244
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 245
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 246
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 247
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 248
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 249
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 250
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 251
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 252
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 253
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 254
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 255
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 268
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 270
SSI Data (SSIDR), offset 0x008 ...................................................................................... 272
Preliminary
LM3S300 Microcontroller
13