LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 60

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LM3S300

Manufacturer Part Number
LM3S300
Description
Lm3s300 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Reset
Reset
Type
Type
System Control
Power-On and Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
60
Bit/Field
31:16
15:2
R/W
RO
1
0
31
15
0
0
R/W
RO
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
30
14
0
1
R/W
RO
29
13
reserved
BORTIM
BORIOR
0
1
BORWT
Name
R/W
RO
28
12
0
1
R/W
RO
27
11
0
1
Type
R/W
R/W
R/W
RO
R/W
RO
26
10
0
1
0x1FFF
R/W
RO
Reset
25
0
9
1
0x0
BORTIM
0
1
Preliminary
R/W
RO
24
0
8
1
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Time Delay
This field specifies the number of internal oscillator clocks delayed before
the BOR output is resampled if the BORWT bit is set.
The width of this field is derived by the t
internal oscillator (IOSC) frequency of 12 MHz ± 30%. At +30%, the
counter value has to exceed 7,800.
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
BOR Wait and Check for Noise
This bit specifies the response to a brown-out signal assertion if BORIOR
is not set.
If BORWT is set to 1 and BORIOR is cleared to 0, the controller waits
BORTIM IOSC periods and resamples the BOR output. If still asserted,
a BOR interrupt is signalled. If no longer asserted, the initial assertion
is suppressed (attributable to noise).
If BORWT is 0, BOR assertions do not resample the output and any
condition is reported immediately if enabled.
R/W
RO
23
0
7
1
R/W
RO
22
0
6
1
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
R/W
RO
19
0
3
1
BOR
width of 500 μs and the
R/W
RO
18
0
2
1
BORIOR
R/W
RO
17
0
1
0
June 04, 2008
BORWT
R/W
RO
16
0
0
1

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