LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 221

no-image

LM3S300

Manufacturer Part Number
LM3S300
Description
Lm3s300 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S300-EQN25-C2
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S300-EQN25-C2T
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S300-IGZ25-C2
Manufacturer:
TI
Quantity:
982
Company:
Part Number:
LM3S300-IGZ25-C2
Quantity:
168
Part Number:
LM3S300-IQN25-C2
Quantity:
250
Part Number:
LM3S300-IQN25-C2
Manufacturer:
TI
Quantity:
214
Part Number:
LM3S300-IQN25-C2
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S300-IQN25-C2T
Manufacturer:
Texas Instruments
Quantity:
10 000
11.2.6
11.3
June 04, 2008
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 241).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 238) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 240).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 242).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 234). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the
RCGC1 register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 219, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 230) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 231) is calculated by the equation:
Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
115200 baud rate
Data length of 8 bits
One stop bit
No parity
FIFOs disabled
No interrupts
Preliminary
LM3S300 Microcontroller
221

Related parts for LM3S300