LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 117

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LM3S300

Manufacturer Part Number
LM3S300
Description
Lm3s300 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Reset
Reset
Type
Type
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x18
June 04, 2008
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
RO
RO
Register 7: USec Reload (USECRL), offset 0x140
Note:
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
USEC
Offset is relative to System Control base address of 0x400F.E000
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x18
0
9
0
0x0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x18 (24 MHz) whenever the flash is being erased or programmed.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
1
USEC
R/W
RO
19
0
3
1
LM3S300 Microcontroller
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
117

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