LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 8

• Manufacturer Part Number: LM3S1150
• Description: Lm3s1150 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 313
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 314
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 314
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
8
Stellaris
CPU Block Diagram ......................................................................................................... 38
TPIU Block Diagram ........................................................................................................ 39
JTAG Module Block Diagram ............................................................................................ 49
Test Access Port State Machine ....................................................................................... 52
IDCODE Register Format ................................................................................................. 57
BYPASS Register Format ................................................................................................ 58
Boundary Scan Register Format ....................................................................................... 58
External Circuitry to Extend Reset .................................................................................... 60
Power Architecture .......................................................................................................... 62
Main Clock Tree .............................................................................................................. 64
Hibernation Module Block Diagram ................................................................................. 121
Clock Source Using Crystal ............................................................................................ 122
Clock Source Using Dedicated Oscillator ......................................................................... 123
Flash Block Diagram ...................................................................................................... 140
GPIO Port Block Diagram ............................................................................................... 165
GPIODATA Write Example ............................................................................................. 166
GPIODATA Read Example ............................................................................................. 166
GPTM Module Block Diagram ........................................................................................ 206
16-Bit Input Edge Count Mode Example .......................................................................... 210
16-Bit Input Edge Time Mode Example ........................................................................... 211
16-Bit PWM Mode Example ............................................................................................ 212
WDT Module Block Diagram .......................................................................................... 241
UART Module Block Diagram ......................................................................................... 265
UART Character Frame ................................................................................................. 266
IrDA Data Modulation ..................................................................................................... 268
SSI Module Block Diagram ............................................................................................. 305
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 308
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 308
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 309
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 309
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 310
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 311
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 311
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 312
I
I
START and STOP Conditions ......................................................................................... 343
Complete Data Transfer with a 7-Bit Address ................................................................... 344
R/S Bit in First Byte ........................................................................................................ 344
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 347
2
2
C Block Diagram ......................................................................................................... 342
C Bus Configuration .................................................................................................... 343
®
1000 Series High-Level Block Diagram ............................................................... 30
Preliminary
2
C Bus ............................................................... 344
July 26, 2008