LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 139
![no-image](/images/no-image-200.jpg)
LM3S1150
Manufacturer Part Number
LM3S1150
Description
Lm3s1150 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1150.pdf
(513 pages)
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Reset
Reset
Type
Type
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset 0x0000.0000
July 26, 2008
Bit/Field
31:0
R/W
R/W
31
15
0
0
R/W
R/W
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store any non-volatile state data and will not lose power during a power
cut operation.
Note:
30
14
0
0
R/W
R/W
29
13
0
0
Name
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of t
accesses. See “Register Access Timing” on page 121.
RTD
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
Type
R/W
R/W
R/W
26
10
0
0
0x0000.0000
Reset
R/W
R/W
25
0
9
0
Preliminary
R/W
R/W
24
0
8
0
Description
Hibernation Module NV Registers[63:0]
RTD
RTD
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
HIB_REG_WRITE
R/W
R/W
20
0
4
0
LM3S1150 Microcontroller
R/W
R/W
19
0
3
0
between write
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0
139
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