LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 364
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LM3S1150
Manufacturer Part Number
LM3S1150
Description
Lm3s1150 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1150.pdf
(513 pages)
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Reset
Reset
Type
Type
Inter-Integrated Circuit (I
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
364
Bit/Field
31:1
0
RO
RO
31
15
0
0
Register 6: I
This register specifies whether an interrupt is pending.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
RIS
2
C) Interface
RO
RO
28
12
0
0
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
Preliminary
reserved
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
July 26, 2008
RO
RO
17
0
1
0
2
RO
RIS
RO
16
C
0
0
0
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