LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 15
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LM3S1150
Manufacturer Part Number
LM3S1150
Description
Lm3s1150 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1150.pdf
(513 pages)
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Synchronous Serial Interface (SSI) ............................................................................................ 305
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Inter-Integrated Circuit (I
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July 26, 2008
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 281
UART Control (UARTCTL), offset 0x030 ......................................................................... 283
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 285
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 287
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 289
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 290
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 291
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 293
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 294
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 295
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 296
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 297
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 298
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 299
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 300
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 301
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 302
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 303
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 304
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 317
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 319
SSI Data (SSIDR), offset 0x008 ...................................................................................... 321
SSI Status (SSISR), offset 0x00C ................................................................................... 322
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 324
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 325
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 327
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 328
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 329
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 330
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 331
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 332
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 333
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 334
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 335
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 336
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 337
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 338
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 339
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 340
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 341
I
I
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I
2
2
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2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 356
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 357
C Master Data (I2CMDR), offset 0x008 ......................................................................... 361
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 362
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 363
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 364
2
C) Interface ........................................................................................ 342
Preliminary
LM3S1150 Microcontroller
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