VG36641641DT-6 Powerchip, VG36641641DT-6 Datasheet - Page 3

• Manufacturer Part Number: VG36641641DT-6
• Description: CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

Pin Function
CLK
CKE
/CS
/RAS, /CAS,
/WE
A0 - A13
BA0,BA1
DQM, UDQM ,
LDQM
DQ0 - DQ15
V
V
VIS
DD,
DDQ,
Document :1G5-0177
V
Symbol
V
SS
SSQ
Supply Power Supply for the memory array and peripheral circuitry
Supply Power Supply are supplied to the output buffers only
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Other input signals are referenecd to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any bank).
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when CS# is registered HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is considered part of
the command code.
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being
entered.
Address Inputs: Provide the row address for ACTIVE command, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank.
The row address is specified by A0-A11.
The column address is specified by A0-A9 (X4) / A0-A8 (X8) / A0-A7 (X16)
Bank Address Inputs: BA0 and BA1 define which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied to.
Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is
masked. When DQM is is high in burst read, Dout is disable at the next but one cycle.
Data Input / Output: Data bus
VG36644041DT / VG36648041DT / VG36641641DT
Rev.5
Function
CMOS Synchronous Dynamic RAM
Page 3