VG36641641DT-6 Powerchip, VG36641641DT-6 Datasheet - Page 22

• Manufacturer Part Number: VG36641641DT-6
• Description: CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
9.3 Write to Read Command Interval
will be written. The data bus must be Hi-Z at least one cycle prior to the first D
WRITE to READ Command Interval
9.4 Read to Write Command Interval
bus must be Hi-Z using DQM before Write.
Document :1G5-0177
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
CLK
T0
WRITE A
Write A
DA0
DA0
1 cycle
T1
Read B
Read B
Hi-Z
Hi-Z
T2
VG36644041DT / VG36648041DT / VG36641641DT
Rev.5
T3
QB0
T4
OUT
CMOS Synchronous Dynamic RAM
.
QB1
QB0
T5
QB2
QB1
T6
QB3
QB2
Page 22
T7
Burst lengh=4
QB3
T8