VG36641641DT-6 Powerchip, VG36641641DT-6 Datasheet - Page 25

• Manufacturer Part Number: VG36641641DT-6
• Description: CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
VIS
Precharge Termination in READ Cycle
Document :1G5-0177
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
CAS latency=2
DQ
CAS latency=3
DQ
CLK
Command
command
T0
Read
Read
T1
RP
T2
from the precharge command.
Q0
VG36644041DT / VG36648041DT / VG36641641DT
Rev.5
T3
Q1
Q0
T4
PRE
PRE
Q2
Q1
CMOS Synchronous Dynamic RAM
T5
t
RP
Q2
Q3
T6
t
RP
ACT
Q3
Hi-Z
T7
Page 25
Burst lengh= X
ACT
Hi-Z
T8