IDT72V3634L15PF IDT, Integrated Device Technology Inc, IDT72V3634L15PF Datasheet

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IDT72V3634L15PF

Manufacturer Part Number
IDT72V3634L15PF
Description
IC FIFO 512X36X2 15NS 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3634L15PF

Function
Asynchronous, Synchronous
Memory Size
36.8K (512 x 36 x 2)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3634L15PF
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©
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
EFA/ORA
2009 Integrated Device Technology, Inc.
FS1/SEN
Memory storage capacity:
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB
flags functions) or First Word Fall Through Timing (using ORA,
ORB, IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
FFA/IRA
FS0/SD
MRS1
A
MBF2
PRS1
CLKA
W/RA
SPM
IDT72V3624–256 x 36 x 2
IDT72V3634–512 x 36 x 2
IDT72V3644–1,024 x 36 x 2
MBA
0
CSA
ENA
AFA
AEA
-A
35
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
36
36
All rights reserved. Product specifications subject to change without notice.
10
3.3 VOLT CMOS SyncBiFIFO
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
FIFO1
FIFO2
Programmable Flag
Offset Registers
36
Pointer
Pointer
Read
Write
36
Status Flag
Status Flag
RAM ARRAY
1,024 x 36
RAM ARRAY
1,024 x 36
256 x 36
512 x 36
256 x 36
512 x 36
Register
Register
Mail 1
Mail 2
Logic
Logic
Pointer
Pointer
1
Timing
Read
Write
Mode
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36
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723624/723634/723644
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
36
TM
36
FEBRUARY 2009
36
FIFO2,
Mail2
Reset
Logic
Control
Port-B
Logic
IDT72V3624
IDT72V3634
IDT72V3644
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4664 drw01
MBF1
EFB/ORB
AEB
FWFT
B
FFB/IRB
AFB
MRS2
PRS2
0
-B
DSC-4664/5
35

Related parts for IDT72V3634L15PF

IDT72V3634L15PF Summary of contents

Page 1

FEATURES: • • • • • Memory storage capacity: IDT72V3624–256 IDT72V3634–512 IDT72V3644–1,024 • • • • • Clock frequencies up to 100 MHz (6.5ns access time) • • ...

Page 2

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 DESCRIPTION: The IDT72V3624/72V3634/72V3644 are pin and functionally compatible versions of the IDT723624/723634/723644, designed to run off a 3.3V supply for exceptionally ...

Page 3

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to ...

Page 4

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A Almost- ...

Page 5

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O FS1/SEN Flag Offset Select 1/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag ...

Page 6

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input Voltage ...

Page 7

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading ...

Page 8

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial 3.3V +/- 0.30V; for 10ns (100 ...

Page 9

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Commercial 3.3V +/- 0.30V; for 10ns ...

Page 10

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 SIGNAL DESCRIPTION MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by providing a LOW pulse ...

Page 11

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset ...

Page 12

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from ...

Page 13

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes) Number of Words in FIFO Memory (3) IDT72V3624 IDT72V3634 0 ...

Page 14

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array. For both ...

Page 15

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 BUS SIZING The Port B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for ...

Page 16

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 BYTE ORDER ON PORT A: BYTE ORDER ON PORT SIZE SIZE H H ...

Page 17

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKA CLKB t RSTS MRS1 BE/FWFT SPM FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 NOTES: 1. ...

Page 18

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKA 1 4 MRS1, MRS2 t FSS t FSH SPM t t FSS FSH 0,0 FS1,FS0 FFA/IRA ENA A0-A35 CLKB FFB/IRB ...

Page 19

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLK t CLKH t CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS2 W/RA t ENS2 MBA t ENS2 ENA ...

Page 20

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 DATA SIZE TABLE FOR WORD WRITES TO FIFO2 (1) SIZE MODE BM SIZE ...

Page 21

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode B0-B35 (FWFT ...

Page 22

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV ...

Page 23

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKA CSA LOW W/RA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IRA HIGH ...

Page 24

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKA CSA LOW W/RA HIGH t t ENS2 ENH MBA t t ENH ENS2 ENA FFA HIGH ...

Page 25

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH ...

Page 26

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENS2 ENH ENB FFB HIGH ...

Page 27

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0-B35 Previous Word ...

Page 28

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous Word ...

Page 29

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous Word ...

Page 30

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKA t ENS2 t ENH ENA t SKEW2 CLKB AEB X1 Words in FIFO1 ENB NOTES: is the minimum time between ...

Page 31

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB t t ENS2 ENB t AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES: is the minimum time between a rising ...

Page 32

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB t ENS1 CSB t ENS2 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t ...

Page 33

IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5V Input Data, 1.5V Enable Input VOLTAGE WAVEFORMS SETUP ...

Page 34

ORDERING INFORMATION XXXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 12/12/2000 pg. ...

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