IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet
IDT72V36100
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IDT72V36100 Summary of contents
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... READ POINTER 65,536 x 36, 131,072 x36 OUTPUT REGISTER Q -Q (x36, x18 or x9 IDT72V3640, IDT72V3650 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 IDT72V36100, IDT72V36110 LD SEN FF/IR PAF EF/OR PAE FLAG HF LOGIC FWFT/SI PFM FSEL0 FSEL1 READ RT ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/ 72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In- ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 RCLK when REN is asserted. An Output Enable (OE) ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 asserted and updated on the rising edge of WCLK only ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 Symbol Name I/O D –D Data Inputs I Data inputs ...
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... Input Low Voltage Com’l/Ind’l — — Operating Temperature 0 — Commercial Operating Temperature -40 — Industrial = - +85 C; JEDEC JESD8-A compliant) A IDT72V3640L IDT72V3650L IDT72V3660L IDT72V3670L IDT72V3680L IDT72V3690L IDT72V36100L IDT72V36110L Commercial and Industrial ( 7.5, 10 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — 40 — ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES = - +85 C; JEDEC JESD8-A compliant) A Com’l & Ind’l IDT72V3640L10 IDT72V3640L15 IDT72V3650L10 IDT72V3650L15 IDT72V3660L10 IDT72V3660L15 IDT72V3670L10 IDT72V3670L15 IDT72V3680L10 IDT72V3680L15 IDT72V3690L10 IDT72V3690L15 IDT72V36100L10 IDT72V36100L15 IDT72V36110L10 IDT72V36110L15 Min. Max. Min. — 100 — — 15 4.5 — 6 4.5 — ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels ...
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... IDT72V3660 and (8,193-m) writes for the IDT72V3670, 16,385 writes for the IDT72V3680, 32,769 writes for the IDT72V3690, 65,537 writes for the IDT72V36100 and 131,073 writes for the IDT72V36110, where m is the full offset value. The default setting for these values are stated in the footnote of Table 2 ...
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... L X IDT72V3660, 72V3670, 72V3680, 72V3690 LD FSEL1 FSEL0 FSEL1 FSEL0 IDT72V36100, 72V36110 LD FSEL1 FSEL0 FSEL1 FSEL0 NOTES empty offset for PAE. ...
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... L H (n+2) to 2,049 (n+2) to 4,097 L H 2,050 to (4,097-(m+1 4,098 to (8,193-(m+1)) (4,097-m) to 4,096 (8,193-m) to 8,192 L L 4,097 8,193 H L PAF HF PAE OR IR IDT72V36110 IDT72V36100 n n (n+2) to 32,769 (n+2) to 65,537 L H 32,770 to (65,537-(m+1)) 65,538 to (131,073-(m+1 (65,537-m) to 65,536 (131,073-m) to 131,072 H L 65,537 ...
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... WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V3640 IDT72V3650 IDT72V3660 IDT72V3670 IDT72V3680 IDT72V3690 IDT72V36100 IDT72V36110 No Operation Write Memory Read Memory No Operation 4667 drw 06 ...
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... IDT72V3650 12 bits for the IDT72V3660 13 bits for the IDT72V3670 14 bits for the IDT72V3680 15 bits for the IDT72V3690 16 bits for the IDT72V36100 17 bits for the IDT72V36110 Note: All unused bits of the LSB & MSB are don’t care Data Inputs/Outputs ...
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... IDT72V3640 11 bits for the IDT72V3650 12 bits for the IDT72V3660 13 bits for the IDT72V3670 14 bits for the IDT72V3680 15 bits for the IDT72V3690 16 bits for the IDT72V36100 17 bits for the IDT72V36110 Note: All unused bits of the LSB & MSB are don’t care D/Q0 1 ...
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... Full Offset MSB. A total of 20 bits for the IDT72V3640, 22 bits for the IDT72V3650, 24 bits for the IDT72V3660, 26 bits for the IDT72V3670, 28 bits for the IDT72V3680, 30 bits for the IDT72V3690, 32 bits for the IDT72V36100 and 34 bits for the IDT72V36110. See Figure 15, Serial Loading of Program- mable Flag Registers, for the timing diagram for this mode ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 was HIGH before setup. During this period, the ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 DATA Data inputs ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 prevent data overflow in the FWFT mode, IR will ...
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... FIFO (D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110). See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 MRS t RSS REN t RSS WEN t RSS FWFT/SI ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 PRS t RSS REN t RSS WEN t RSS RT ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 WRITE WCLK 1 (1) t SKEW1 ...
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... PAE offset PAF offset and D = maximum FIFO depth 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. 6. First data word latency = t ...
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... LD = HIGH PAE Offset PAF offset and D = maximum FIFO depth 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. (2) ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110 ...
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... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 LOW. ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110 ...
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... for the IDT72V3640 for the IDT72V3650 for the IDT72V3660 for the IDT72V3670 for the IDT72V3680 for the IDT72V3690 for the IDT72V36100 and for the IDT72V36110. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) ...
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... In IDT Standard mode 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. In FWFT mode 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 ...
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... In IDT Standard Mode 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. In FWFT Mode 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 ...
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... In IDT Standard mode maximum FIFO depth 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110 FWFT mode maximum FIFO depth 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 ...
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... IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110 with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 FWFT/SI FWFT/SI WRITE CLOCK WCLK IDT 72V3640 WRITE ENABLE WEN ...
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IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order for speed grades faster than 15ns. 05/25/2000 pgs. and 35. 07/28/2000 pgs. 13, 14 and 34. 12/14/2000 pgs. ...