IDT72V3634L15PF IDT, Integrated Device Technology Inc, IDT72V3634L15PF Datasheet - Page 8

• Manufacturer Part Number: IDT72V3634L15PF
• Description: IC FIFO 512X36X2 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3634L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 36.8K (512 x 36 x 2)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3634L15PF

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial: V
NOTES:
1. For 10ns (100 MHz operation), V
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
DH
CLK
CLKH
CLKL
DS
ENS1
ENS2
FSS
BES
SPMS
SDS
SENS
FWS
ENH
RSTH
FSH
BEH
SPMH
SDH
SENH
SPH
SKEW1
SKEW2
Symbol
RSTS
(3)
(3,4)
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time CSA before CLKA↑; CSB before CLKB↑
Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB
before CLKB↑
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH
Setup Time, BE/FWFT before MRS1 and MRS2 HIGH
Setup Time, SPM before MRS1 and MRS2 HIGH
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
Setup Time, BE/FWFT before CLKA↑
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
Hold Time, SPM after MRS1 and MRS2 HIGH
Hold Time, FS0/SD after CLKA↑
Hold Time, FS1/SEN HIGH after CLKA↑
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
Skew Time between CLKA↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA,
and FFB/IRB
Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
MBB after CLKB↑
CC
= 3.3V +/- 0.30V; for 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V; T
Parameter
A
= 0° to +70°C; JEDEC JESD8-A compliant.
TM
WITH BUS-MATCHING
CC
= 3.3V +/- 0.15V ; T
8
(2)
(2)
A
= 0°Cto +70°C; JEDEC JESD8-A compliant
IDT72V3624L10
IDT72V3634L10
IDT72V3644L10
Min.
4.5
4.5
7.5
7.5
7.5
0.5
0.5
0.5
0.5
10
12
—
3
4
3
5
3
3
0
4
2
2
2
2
5
COMMERCIAL TEMPERATURE RANGE
Max.
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
IDT72V3624L15
IDT72V3634L15
IDT72V3644L15
Min.
4.5
4.5
7.5
7.5
7.5
7.5
—
15
12
6
6
4
5
4
4
0
1
1
4
2
2
2
1
1
2
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns