IDT72V3634L15PF IDT, Integrated Device Technology Inc, IDT72V3634L15PF Datasheet - Page 11

• Manufacturer Part Number: IDT72V3634L15PF
• Description: IC FIFO 512X36X2 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3634L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 36.8K (512 x 36 x 2)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3634L15PF

TABLE 1 — FLAG PROGRAMMING
labeled Y2. The index of each register name corresponds to its FIFO number.
The offset registers can be loaded with preset values during the reset of a FIFO,
programmed in parallel using the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
and FWFT modes.
— PRESET VALUES
one of the three preset values listed in Table 1, the Serial Program Mode (SPM)
and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1, MRS2). For example, to load the
preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when
FlFO1 reset (MRS1) returns HIGH. Flag-offset registers associated with FIFO2
are loaded with one of the preset values in the same way with FIFO2 Master
Reset (MRS2), toggled simultaneously with FIFO1 Master Reset (MRS1). For
relevant preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
Reset on both FlFOs simultaneously with SPM HIGH and FS0 and FS1 LOW
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is
complete, the first four writes to FIFO1 do not store data in the RAM but load
the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by
the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The highest numbered input is
used as the most significant bit of the binary number in each case. Valid
programming values for the registers range from 1 to 252 for the IDT72V3624;
1 to 508 for the IDT72V3634; and 1 to 1,020 for the IDT72V3644. After all the
offset registers are programmed from Port A, the Port B Full/Input Ready flag
(FFB/IRB) is set HIGH, and both FIFOs begin normal operation. Refer to Figure
5 for a timing diagram illustration of parallel programming of the flag offset values.
— SERIAL LOAD
with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SPM
SPM, FS0/SD, and FS1/SEN function the same way in both IDT Standard
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset
H
H
H
H
H
H
H
L
L
L
L
FS1/SEN
H
H
H
H
H
H
L
L
L
L
L
FS0/SD
H
H
H
H
H
H
L
L
L
L
L
MRS1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
MRS2
↑
↑
↑
↑
↑
↑
↑
↑
X
X
X
TM
WITH BUS-MATCHING
Parallel programming via Port A
Serial programming via SD
X1 AND Y1 REGlSTERS
11
transition of MRS1 and MRS2. After this reset is complete, the X and Y register
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. There are 32-, 36-, or 40-
bit writes needed to complete the programming for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The four registers are written in
the order Y1, X1, Y2, and finally, X2. The first-bit write stores the most significant
bit of the Y1 register and the last-bit write stores the least significant bit of the X2
register. Each register value can be programmed from 1 to 252 (IDT72V3624),
1 to 508 (IDT72V3634), or 1 to 1,020 (IDT72V3644).
A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/
IRB) flag also remains LOW throughout the serial programming process, until
all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition
of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure
6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (IDT Standard and FWFT Modes) timing diagram.
FIFO WRITE/READ OPERATION
(CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both CSA and W/RA are LOW.
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on Port A are independent of any concurrent Port B operation.
that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read
select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either CSB is HIGH or W/RB is
Reserved
Reserved
Reserved
When the option to program the offset registers serially is chosen, the Port
The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
The Port B control signals are identical to those of Port A with the exception
64
64
16
16
8
8
(1)
COMMERCIAL TEMPERATURE RANGE
X2 AND Y2 REGlSTERS
Parallel programming via Port A
Serial programming via SD
Reserved
Reserved
Reserved
64
16
X
X
X
8
(2)