IDT72V3634L15PF IDT, Integrated Device Technology Inc, IDT72V3634L15PF Datasheet - Page 5

• Manufacturer Part Number: IDT72V3634L15PF
• Description: IC FIFO 512X36X2 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3634L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 36.8K (512 x 36 x 2)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3634L15PF

PIN DESCRIPTIONS (CONTINUED)
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
FS1/SEN Flag Offset Select 1/
FS0/SD Flag Offset Select 0/
MBA
MBB
MBF1
MBF2
MRS1
MRS2
PRS1
PRS2
SIZE
SPM
W/RA
W/RB
Symbol
Serial Data
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
FIFO1 Partial
Reset
FIFO2 Partial
Reset
Bus Size Select
Serial Programming
Mode
Port-A Write/
Read Select
Port-B Write/
Read Select
Serial Enable,
Name
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of three preset values (8, 16, or 64),
parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous
on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32
for the 72V3624, 36 for the 72V3634, and 40 for the 72V3644. The first bit write stores the Y-register (Y1)
MSB and the last bit write stores the X-register (X2) LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB
when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial
Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA
when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial
Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial
or parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions
of CLKB must occur while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the
Port A output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-
to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port
B. The level of SIZE must be static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming
or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of
CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present
TM
WITH BUS-MATCHING
5
Description
COMMERCIAL TEMPERATURE RANGE