CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 9

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
Applications
Controlling Jitter
Jitter is defined in many ways including: phase noise,
long-term jitter, cycle to cycle jitter, period jitter, absolute jitter,
and deterministic. These jitter terms are usually given in terms
of rms, peak to peak, or in the case of phase noise dBC/Hz
with respect to the fundamental frequency.
Power Supply Noise and clock output loading are two major
system sources of clock jitter. Power Supply noise can be
mitigated by proper power supply decoupling (0.1 µF ceramic
cap 0.25”) of the clock and ensuring a low impedance ground
to the chip. Reducing capacitive clock output loading to a
minimum lowers current spikes on the clock edges and thus
reduces jitter.
Reducing the total number of active outputs will also reduce
jitter in a linear fashion. However, it is better to use two outputs
to drive two loads than one output to drive two loads.
Test Circuit
Figure 6. Duty Cycle Definition; DC = t2/t1
CLK
AV
t3
V
DD
DD
20%
80%
0.1 mF
0.1 mF
t4
OUTPUTS
GND
The rate and magnitude that the PLL corrects the VCO
frequency is directly related to jitter performance. If the rate is
too slow, then long term jitter and phase noise will be poor.
Therefore, to improve long-term jitter and phase noise,
reducing Q to a minimum is advisable. This technique will
increase the speed of the Phase Frequency Detector which in
turn drive the input voltage of the VCO. In a similar manner
increasing P till the VCO is near its maximum rated speed will
also decrease long term jitter and phase noise. For example:
Input Reference of 12 MHz; desired output frequency of
33.3 MHz. One might arrive at the following solution: Set
Q = 3, P = 25, Post Div = 3. However, the best jitter results will
be Q = 2, P = 50, Post Div = 9.
For more information, refer to the application note “Jitter in
PLL-Based Systems: Causes, Effects, and Solutions”
available at http://www.cypress.com/clock/appnotes.html, or
contact your local Cypress field applications engineer.
CLK
Figure 7. Rise and Fall Time Definitions
t6
Figure 8. Peak-to-Peak Jitter
50%
t1
t2
C LOAD
0.1 µF
CLK out
V
DDL
50%
CY22150
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