CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 7

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
Table 11.
Table 12.
Table 13. CLKOE Bit Setting
Programmable Interface Timing
The CY22150 utilizes a 2-wire serial-interface SDAT and
SCLK that operates up to 400 kbits/second in Read or Write
mode. The basic Write serial format is as follows.
Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); eight-bit Memory Address (MA); ACK;
eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK;
eight-bit data in MA+2; ACK; etc. until STOP bit.The basic
serial format is illustrated in Figure 3.
Data Valid
Data is valid when the Clock is HIGH, and may only be transi-
tioned when the clock is LOW, as illustrated in Figure 2.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 4.
CLKSRC2
Address
Address
44H
45H
46H
09H
0
0
0
0
1
1
1
1
CLKSRC1
CLKSRC2
CLKSRC0
CLKSRC1
for LCLK1
for LCLK3
for CLK6
0
0
1
1
0
0
1
1
D7
D7
0
SDAT
SCLK
CLKSRC0
CLKSRC1
CLKSRC2
CLKSRC0
for LCLK1
for LCLK4
for CLK6
0
1
0
1
0
1
0
1
D6
D6
0
Figure 2. Data Valid and Data Transition Periods
V
V
IH
IL
Reference input.
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
Reserved – do not use.
CLKSRC0
CLKSRC1
for LCLK1
for LCLK4
CLK6
D5
D5
CLK
1
Data valid
HIGH
CLKSRC2
CLKSRC0
for LCLK2
for LCLK4
CLK5
D4
D4
1
Transition to next bit
CLK
t
DH
Start Sequence – Start frame is indicated by SDAT going
LOW when SCLK is HIGH. Every time a Start signal is given,
the next eight-bit data must be the device address (seven bits)
and a R/W bit, followed by register address (eight bits) and
register data (eight bits).
Stop Sequence – Stop frame is indicated by SDAT going
HIGH when SCLK is HIGH. A Stop frame frees the bus for
writing to another part on the same bus or writing to another
random register address.
Acknowledge Pulse
During Write mode, the CY22150 will respond with an ACK
pulse after every eight bits. This is accomplished by pulling the
SDAT line LOW during the N*9
Figure 5. (N = the number of eight-bit segments transmitted.)
During Read mode, the ACK pulse after the data packet is sent
is generated by the master.
LOW
t
SU
CLKSRC1
CLKSRC2
for LCLK2
Definition and Notes
for CLK5
LCLK4
D3
D3
1
CLKSRC0
CLKSRC1
for LCLK2
for CLK5
LCLK3
D2
D2
1
th
clock cycle, as illustrated in
CLKSRC2
CLKSRC0
for LCLK3
for CLK5
LCLK2
D1
D1
1
CY22150
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CLKSRC1
CLKSRC2
for LCLK3
for CLK6
LCLK1
D0
D0
1