CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 8

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
SDAT
SCLK
Parameter
CLK
START
CLK
SDAT Write
Multiple
Contiguous
Registers
SDAT Read
Multiple
Contiguous
Registers
f
SCLK
t
t
SU
DH
HIGH
LOW
Start Signal
Start Signal
DA6
Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data
Frequency of SCLK
Start mode time from SDA LOW to SCL LOW
SCLK LOW period
SCLK HIGH period
Data transition to SCLK HIGH
Data hold (SCLK LOW to data transition)
Rise time of SCLK and SDAT
Fall time of SCLK and SDAT
Stop mode time from SCLK HIGH to SDAT HIGH
Stop mode to Start mode
DA5DA0
+
+
R/W = 0
R/W = 0
7-bit
Device
Address
7-bit
Device
Address
1-bit
1-bit
R/W ACK
ACK
ACK
Slave
1-bit
1-bit
Slave
Register
Address
(XXH)
Register
Address
(XXH)
8-bit
8-bit
START
Description
1-bit
Slave
ACK
1-bit
Slave
ACK
Register
Data
(XXH)
7-Bit
Device
Address (XXH)
Figure 3. Data Frame Architecture
8-bit
Figure 4. Start and Stop Frame
RA7
1-bit
Slave
ACK
1-bit
R/W = 1
(XXH+1)
Register
Data
Register
Data
8-bit
8-bit
RA6RA1
+
+
Transition
to next bit
1-bit
Slave
ACK
1-bit
Master
ACK
Register
Data
(XXH+2)
Register
Data
(XXH+1)
8-bit
8-bit
RA0
ACK
1-bit
Slave
ACK
1-bit
Master
ACK
STOP
(FFH)
(FFH)
Register
Data
Register
Data
Min.
8-bit
100
8-bit
0.6
1.3
0.6
0.6
1.3
0
D7
1-bit
Slave
ACK
1-bit
Master
ACK
D6
Register
Data
(00H)
Register
Data
(00H)
8-bit
8-bit
+
+
D1
1-bit
Slave
ACK
1-bit
Master
ACK
SDAT
SCLK
Max.
400
300
300
D0
1-bit
Slave
ACK
1-bit
Master
ACK
ACK
Stop Signal
Stop Signal
CY22150
Page 8 of 13
Unit
kHz
µ
µ
µ
µ
µ
ns
ns
ns
ns
s
s
s
s
s
STOP