CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 6

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
Table 6. P Counter Register Definition
Table 7. P Counter Register Definition
Table 8. PLL Post Divider Options
Table 9. Charge Pump Settings
Table 10. Register 40H Change Pump Bit Settings
Although using the above table will guarantee stability, it is
recommended to use the Print Preview function in
CyClocksRT to determine the correct charge pump settings for
optimal jitter performance.
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use
CyClocksRT to determine the best charge pump setting.
Clock Output Settings: CLKSRC – Clock Output Cross-
point Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)]
CLKOE – Clock Output Enable Control [09H(5..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint
switch matrix defines which source is attached to each
individual clock output. CLKSRC(2..0) is set in Registers 44H,
45H, and 46H. The remainder of register 46H(5:0) must be
written with the values stated in the register table when writing
register values 46H(7:6).
In addition, each clock output has individual CLKOE control,
set by register 09H(5..0).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
Address
Address
Address
Address
OCH
40H
41H
42H
40H
41H
42H
47H
40H
Charge Pump Setting – Pump(2..0)
to
DIV1SRC
DIV2SRC
PB(7)
PB(7)
be
PO
PO
D7
D7
D7
D7
1
1
1
101, 110, 111
rising
000
001
010
100
011
DIV1N(6)
DIV2N(6)
PB(6)
PB(6)
edge
Q(6)
Q(6)
D6
D6
D6
D6
1
1
1
phase-aligned
DIV1N(5)
DIV2N(5)
PB(5)
PB(5)
Q(5)
Q(5)
D5
D5
D5
D5
0
0
0
with
DIV1N(4)
DIV2N(4)
Pump(2)
Pump(2)
Pump(2)
PB(4)
PB(4)
Q(4)
Q(4)
D4
D4
D4
D4
guaranteed
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in Table 13.
The output swing of LCLK1 through LCLK4 is set by V
output swing of CLK5 and CLK6 is set by V
Test, Reserved, and Blank Registers
Writing to any of the following registers will cause the part to
exhibit abnormal behavior, as follows.
[00H to 08H]
[0AH to 0BH]
[0DH to 11H]
[14H to 3FH]
[43H]
[48H to FFH]
DIV1N(3)
DIV2N(3)
Pump(1)
Pump(1)
Pump(1)
PB(3)
PB(3)
Do not use – device will be unstable
Q(3)
Q(3)
D3
D3
D3
D3
to
to
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved.
Calculated P
be
be
DIV1N(2)
DIV2N(2)
Pump(0)
Pump(0)
Pump(0)
800 – 1023
480 – 639
640 – 799
PB(2)
PB(2)
45 – 479
Q(2)
Q(2)
16 – 44
rising
rising
D2
D2
D2
D2
edge
edge
total
DIV1N(1)
DIV2N(1)
PB(9)
PB(1)
PB(9)
PB(1)
PB(9)
Q(1)
Q(1)
D1
D1
D1
D1
phase-aligned
phase-aligned
DD
CY22150
.
Page 6 of 13
DIV1N(0)
DIV2N(0)
PB(8)
PB(0)
PB(8)
PB(0)
PB(8)
Q(0)
Q(0)
DDL
D0
D0
D0
D0
. The
with
with