CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 11

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
Table 17. AC Electrical Characteristics
Device Characteristics
Ordering Information
Ordering Code
CY22150FC
CY22150FI
CY22150ZC-xxx
CY22150ZI-xxx
CY3672
CY3672ADP000
Notes:
10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
Parameter
7.
8.
9.
Parameter
Complexity
Not 100% tested, guaranteed by design.
Skew value guaranteed when outputs are generated from the same divider bank. See Logic Diagram for more information.
Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, V
“PLL-Based Systems: Causes, Effects, and Solutions,” available at http://wwww.cypress.com/clock/appnotes.html, or contact your local Cypress field appli-
cations engineer).
100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
t2
t3
t4
t2
t3
t4
t5
t6
t10
t1
LO
LO
LO
[8]
[9]
θ
HI
HI
HI
JA
[7]
[10]
Output Frequency,
Commercial Temp
Output Frequency,
Industrial Temp
Output Duty Cycle
Output Duty Cycle
Rising Edge Slew
Rate (V
Falling Edge Slew
Rate (V
Rising Edge Slew
Rate (V
Falling Edge Slew
Rate (V
Skew
Clock Jitter
PLL Lock Time
[10]
Name
DDL
DDL
DDL
DDL
Package Name
Z16
Z16
Z16
Z16
FTG Development System N/A
CY22150F Socket
= 2.5V)
= 2.5V)
= 3.3V)
= 3.3V)
Transistor Count
theta JA
Name
Clock output limit, 3.3V
Clock output limit, 2.5V
Clock output limit, 3.3V
Clock output limit, 2.5V
Duty cycle is defined in Figure 6; t1/t2
fOUT < 166 MHz, 50% of V
Duty cycle is defined in Figure 6; t1/t2
fOUT > 166 MHz, 50% of V
Output clock rise time, 20% – 80% of V
Defined in Figure 7.
Output dlock fall time, 80% – 20% of V
Defined in Figure 7.
Output dlock rise time, 20% – 80% of
V
Output dlock fall time, 80% – 20% of
V
Output-output skew between related outputs.
Peak-to-peak period jitter
DD
DD
/V
/V
DDL
DDL
. Defined in Figure 7.
. Defined in Figure 7.
Package Type
16-lead TSSOP
16-lead TSSOP
16-lead TSSOP
16-lead TSSOP
Description
DD
DD
74,600
Value
115
Operating Range
Commercial (0 to 70°C)
Industrial (–40 to 85°C)
Commercial (0 to 70°C)
Industrial (–40 to 85°C)
DDL
DDL
.
.
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
Min.
0.6
0.6
0.8
0.8
45
40
Typ.
0.30
250
1.2
1.2
1.4
1.4
50
50
transistors
Operating Voltage
DDL
°C/W
Unit
, (2.5V or 3.3V jitter in
CY22150
166.6
166.6
Max.
200
150
250
55
60
Page 11 of 13
3.3V
3.3V
3.3V
3.3V
3
MHz
MHz
MHz
MHz
Unit
V/ns
V/ns
V/ns
V/ns
ms
ps
ps
%
%