CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 5

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
Input Load Capacitors
Input load capacitors allow the user to set the load capacitance
of the CY22150 to match the input load capacitance from a
crystal. The value of the input load capacitors is determined by
8 bits in a programmable register [13H]. Total load capacitance
is determined by the formula:
CapLoad = (CL– CBRD – CCHIP)/0.09375 pF
where:
In CyclocksRT, only the crystal capacitance (C
C
capacitance is higher or lower than 2 pF, the formula above
can be used to calculate a new CapLoad value and
programmed into register 13H.
In CyClocksRT, enter the crystal capacitance (C
of CapLoad will be determined automatically and programmed
into the CY22150. Through the SDAT and SCLK pins, the
value can be adjusted up or down if your board capacitance is
greater or less than 2 pF. For an external clock source,
CapLoad defaults to 0. See Table 5 for CapLoad bit locations
and values.
The input load capacitors are placed on the CY22150 die to
reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when non-linear load capacitance is affected
by load, bias, supply and temperature changes.
PLL Frequency, Q Counter [42H(6..0)]
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Q
Q
Q
The minimum value of Q
is 129. Register 42H is defined in the table.
Stable operation of the CY22150 cannot be guaranteed if
REF/Q
are defined in Table 6.
PLL Frequency, P Counter [40H(1..0)],
[41H(7..0)], [42H(7)
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q
VCO frequency. The product counter, defined as P
Table 5. Input Load Capacitor Register Bit Settings
• C
• C
• C
• 0.09375 pF = the step resolution available due to the 8-bit
CHIP
total
total
Address
itors and board trace capacitance. In CyClocksRT, this value
defaults to 2 pF.
register.
L
BRD
CHIP
13H
is defined by the formula:
= Q + 2
= specified load capacitance of your crystal.
is set to 6 pF, and C
total
= the total board capacitance, due to external capac-
= 6 pF.
falls below 250 kHz. Q
CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
D7
total
BRD
is 2. The maximum value of Q
defaults to 2 pF. If your board
total
D6
total
bit locations and values
) value to achieve the
L
) is specified.
D5
L
). The value
total
total
total
, is
.
D4
made up of two internal variables, PB and PO. The formula for
calculating P
P
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see Section 5). The 3 MSBs of register
40H are preset and reserved and cannot be changed. PO is a
single bit variable, defined in register 42H(7). This allows for
odd numbers in P
The remaining seven bits of 42H are used to define the Q
counter, as shown in Table 6.
The minimum value of P
is 2055. To achieve the minimum value of P
should both be programmed to 0. To achieve the maximum
value of P
should be programmed to 1.
Stable operation of the CY22150 cannot be guaranteed if the
value of (P
100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
PLL Post Divider Options [OCH(7..0)], [47H(7..0)]
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal
feeding into the divider banks is the calculated VCO frequency
or REF. There are two select muxes (DIV1SRC and DIV2SRC)
and two divider banks (Divider Bank 1 and Divider Bank 2)
used to determine this clock signal. The clock signal passing
through DIV1SRC and DIV2SRC is referred to as DIV1CLK
and DIV2CLK, respectively.
The divider banks have 4 unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-
dently programmed (DIV1N and DIV2N) for each of the two
divider banks. The minimum value of DIVxN is 4. The
maximum value of DIVxN is 127. A value of DIVxN below 4 is
not guaranteed to work properly.
DIV1SRC is a single bit variable, controlled by register OCH.
The remaining seven bits of register OCH determine the value
of post divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H.
The remaining seven bits of register 47H determine the value
of post divider DIV2N.
Register OCH and 47H are defined in Table 8.
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
are dependent on internal variable PB (see “PLL Frequency,
P Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 9 summa-
rizes the proper charge pump settings, based on Ptotal.
See Table 10 for register 40H bit locations and values.
total
= (2(PB + 4) + PO).
D3
total
total
total
, PB should be programmed to 1023, and PO
*(REF/Q
is:
total
.
total
total
D2
)) is above 400 MHz or below
is 8. The maximum value of P
D1
total
CY22150
Page 5 of 13
, PB and PO
D0
total