AN1740 Freescale Semiconductor / Motorola, AN1740 Datasheet - Page 60

• Manufacturer Part Number: AN1740
• Description: Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers
• Manufacturer: Freescale Semiconductor / Motorola

Application Note
Analog Interrupt
Timing
Instruction Cycle
Timing
60
timers with respect to the instruction cycles. These sources of timing
“jitter” will degrade the accuracy of the readings.
The conversion can be timed with a combination of software start of the
charging ramp and an analog interrupt which reads the 16-bit timer or
multifunction timer. This mode of operation will allow other tasks to be
performed while the conversion is in progress, which is especially useful
for long conversions. However, the accuracy of the analog interrupt in
capturing the ending time means that all other interrupts may not be
active until after the conversion is complete.
Also, once the analog interrupt is entered, the time that is read must be
corrected for the minimum interrupt latency time to get into the analog
interrupt service routine and read the timer state. This latency, and,
therefore, the accuracy of the time, will be affected by the variation in
cycle times of all instruction types used in the particular application
software. Avoiding long cycle time instructions such as JSR, SWI, MUL,
and some indexed addressing modes can reduce this variation from nine
to three bus cycles.
The user should be aware of the exact cycle when hardware changes
and data reads occur when using the manual A/D conversion
techniques. The accuracy of the software timing and the “rounding” of
the time count will depend on knowing the precise cycle and clock edge
when the charge time begins and when the voltage comparator output is
sampled. Two examples of simple mode 0 flows are shown in
In the flow for ATDGO1, a simple loop checks for the CPF2 flag and
increments the accumulator. The flow for ATDGO2 includes some
added delays to position the first check of the CPF2 flag to be one-half
the number of the bus cycles that occur in each loop that follows. This
places the CPF2 flag check at one-half of a “bit time” for proper rounding
of partial bits. The details of these two examples are given in the two
following software examples, and the timing is shown in
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Figure
MOTOROLA
Figure
28.
AN1740
27.