AN1740 Freescale Semiconductor / Motorola, AN1740 Datasheet - Page 23

• Manufacturer Part Number: AN1740
• Description: Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers
• Manufacturer: Freescale Semiconductor / Motorola

Comparator
Output Analog
Interrupt
AN1740
MOTOROLA
The outputs of the comparators can be monitored also by using the
analog interrupt. When using interrupt-driven detection of the transitions,
the main consideration is the latency of entering the interrupt service
routine and its later return to the background software. The CPU will
always complete the instruction currently in process before beginning an
interrupt service routine. The range of instruction times varies from two
to 11 CPU bus cycles.
The three longest instructions are the MUL (11 cycles), the SWI (10
cycles), and the RTI (nine cycles). While the user can avoid using either
the MUL or SWI instruction, the RTI is a necessary instruction if
interrupts are being considered.
Once the interrupt is acknowledged, there is a delay of 10 cycles to stack
the CPU state before executing the first instruction in the interrupt
service routine. This means it takes from 12 to 21 cycles to acknowledge
the interrupt and access its service routine. Once the service routine is
completed, there will be nine cycles to execute its final RTI instruction
and 10 more cycles to unstack the CPU state before the interrupt is
complete and the CPU is ready to begin processing another one.
From this discussion, at least 46 CPU bus cycles are required to simply
acknowledge and clear the CPF1 or CPF2 static flags as follows:
This does include any software time to actually perform a task.
Therefore, analog interrupts should not be used to detect pulses
separated by less than about 60 CPU bus cycles. On the other hand,
software polling can test and clear the CPF1 or CPF2 static flags within
11 CPU bus cycles as follows:
Software polling should not be used for pulses separated by less than 30
CPU bus cycles.
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Freescale Semiconductor, Inc.
For More Information On This Product,
21 cycles to acknowledge; max instruction plus stacking
Six cycles to clear the static flag (BSET)
19 cycles to return; RTI plus unstacking
Five cycles to test for the static flag being set (BRSET)
Six cycles to clear the static flag (BSET)
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Voltage Comparators
Application Note
23