LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 78

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
78
Reset
Reset
Type
Type
Bit/Field
31:29
28:23
22:7
6:4
3:0
RO
RO
31
15
0
0
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
reserved
RO
RO
30
14
0
0
DSDIVORIDE
DSOSCSRC
reserved
reserved
reserved
Name
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
R/W
RO
28
12
0
0
reserved
R/W
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
R/W
DSDIVORIDE
RO
26
10
1
0
Reset
0x0F
0
0
0
0
R/W
RO
25
1
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, forces IOSC to be clock source during Deep Sleep mode.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
RO
Name
NOORIDE
IOSC
30kHz
32kHz
24
1
8
0
R/W
RO
23
1
7
0
Value
0
1
3
7
R/W
RO
22
0
6
0
Description
No override to the oscillator clock source is done
Use internal 12 MHz oscillator as source
Use 30 kHz internal oscillator
Use 32 kHz external oscillator
DSOSCSRC
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
reserved
RO
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
June 14, 2007
RO
RO
17
0
1
0
RO
RO
16
0
0
0