LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 392

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Pulse Width Modulator (PWM)
PWM0 Interrupt Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
392
Reset
Reset
Type
Type
Bit/Field
31:6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4
These registers control the interrupt generation capabilities of the PWM generators (PWM0INTEN
controls the PWM generator 0 block, and so on). The events that can cause an interrupt are:
■
■
■
■
■
■
Any combination of these events can generate either an interrupt.
RO
RO
The counter being equal to the load register
The counter being equal to zero
The counter being equal to the comparator A register while counting up
The counter being equal to the comparator A register while counting down
The counter being equal to the comparator B register while counting up
The counter being equal to the comparator B register while counting down
30
14
0
0
IntCntLoad
IntCntZero
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
reserved
Name
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
reserved
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the PWMnLOAD
register.
When 1, an interrupt occurs when the counter is 0.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
IntCmpBD
R/W
RO
21
0
5
0
IntCmpBU
R/W
RO
20
0
4
0
IntCmpAD
R/W
RO
19
0
3
0
IntCmpAU
R/W
RO
18
0
2
0
June 14, 2007
IntCntLoad
R/W
RO
17
0
1
0
IntCntZero
R/W
RO
16
0
0
0