LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 349

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x018
Type RO, reset 0x0000.0000
June 14, 2007
Reset
Reset
Type
Type
Bit/Field
31:1
0
RO
RO
31
15
0
0
Register 7: I
This register specifies whether an interrupt was signaled.
RO
RO
30
14
0
0
reserved
Name
MIS
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
2
RO
RO
28
12
0
0
C Master Masked Interrupt Status (I2CMMIS), offset 0x018
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
26
10
0
0
Reset
0
0
RO
RO
25
0
9
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
This bit specifies the raw interrupt state (after masking) of the I
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S1150 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
2
C master
MIS
RO
RO
16
0
0
0
349