LM3S1150-IQC50 Luminary Micro, Inc., LM3S1150-IQC50 Datasheet - Page 300

• Manufacturer Part Number: LM3S1150-IQC50
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Synchronous Serial Interface (SSI)
13.3
300
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 13-12 on page 300 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1.
2.
3.
SSIRx
SSITx
SSIRx
Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
Select whether the SSI is a master or slave:
a.
b.
c.
Configure the clock prescale divisor by writing the SSICPSR register.
For master operations, set the SSICR1 register to 0x00000000.
For slave mode (output enabled), set the SSICR1 register to 0x00000004.
For slave mode (output disabled), set the SSICR1 register to 0x0000000C.
LSB
0
Luminary Micro Confidential-Advance Product Information
MSB
output data
4 to 16 bits
LSB
MSB
t
Hold
=t
t
Setup
SSIClk
8-bit control
=(2*t
SSIClk
)
First RX data to be
sampled by SSI slave
LSB
MSB
June 14, 2007